Senior CAD Infra Engineer

Job description

In most instances, this position requires in-person interviews as part of the hiring process. Minimum qualifications:
• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
• 8 years of experience with scripting for automation (e.g., shell, Python).
Preferred qualifications:
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
• Experience in software expertise to develop the hardware automations for physical design automation, and their software integration in our automated flow.
• Experience in propose, design and implement software automation that directly addresses bottlenecks in today's ASIC and SoC EDA flow.
• Working experience in advanced technology nodes.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
• Work with partner teams to provide the compute, storage, and methodology needs of the chip design, verification, and physical design teams. Collaborate with Application-Specific Integrated Circuit (ASIC) teams to implement tools and methodologies.
• Design and implement CAD tools, solutions, and methodologies for ASIC development. Extend the capabilities of third-party tools through their dedicated APIs.
• Propose, design, and implement software automation that directly addresses bottlenecks in today's ASIC and SoC EDA flow. Lead and actively contribute to the automation and integration of physical design (floorplanning, power planning, synthesis, place and route, clock tree synthesis, timing closure, STA, DRC, LVS, DFM, etc.) in our automated flow.
• Leverage your software expertise to develop the hardware automations required for physical design automation, and their software integration in our automated flow.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .